Display panel, method for detecting the same and detection system

ABSTRACT

A display panel includes M drive groups disposed side by side in a display area, and M pad groups disposed in a wiring area around the display area. Each pad group includes N data detection terminals. Each drive group includes a plurality of columns of pixel units, and each pixel unit includes N sub-pixels. N≥3, M≥2, and M and N are positive integers. Each data detection terminal is configured to receive a signal output from a detection device. The pad groups are in one-to-one correspondence with the drive groups. Sub-pixels having same color in a drive group of the drive groups are electrically connected to a data detection terminal of one of the pad groups corresponding to the drive group via a same one of data lines.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Chinese Patent Application No.201710856173.7, filed on Sep. 19, 2017, titled “A DISPLAY PANEL, METHODFOR DETECTING THE SAME AND DETECTION SYSTEM”, the entire content ofwhich is hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, andin particular, to a display panel, a method for detecting the same and adetection system.

BACKGROUND

As a current-mode light-emitting device, Organic Light Emitting Diode(OLED) or Light Emitting Diode (LED) is increasingly used in thehigh-performance display field due to its characteristics such asself-illumination, fast response, wide viewing angle and the ability ofbeing fabricated on a flexible substrate, and etc.

SUMMARY

In one aspect, a display panel is provided, and the display panelincludes M drive groups disposed side by side in a display area and Mpad groups disposed in a wiring area around the display area. Each drivegroup includes a plurality of columns of pixel units, and each pixelunit includes N sub-pixels, wherein, N is greater than or equal to 3, Mis greater than or equal to 2, and M and N are positive integers. Eachpad group includes N data detection terminals, and each data detectionterminal is configured to receive a signal output by a detection device.The pad groups are in one-to-one correspondence with the drive groups.Sub-pixels having same color in a drive group of the drive groups areelectrically connected to a data detection terminal of one of the padgroups corresponding to the drive group via data lines.

In some embodiments, the display panel further includes a plurality ofread detection terminals disposed in the wiring area, and a plurality ofread lines. Each read line is connected to one of the plurality of readdetection terminals, and pixel circuits of sub-pixels in each pixel unitis connected to a same read line. The read line is configured to collectthreshold voltages of drive transistors in the pixel circuits, andoutput the threshold voltages to the detection device via acorresponding read detection terminal.

In some embodiments, the display panel further includes a plurality ofshort wirings in the wiring area. An end of each short wiring isconnected to a corresponding one of the data detection terminals, and anopposite end is connected to a corresponding one of the data lines.

In some embodiments, the display panel further includes gate linesdisposed in the display area. The gate lines and the data linesintersect, and are in a same layer and of a same material.

In some embodiments, a pixel circuit of each sub-pixel in the displayarea includes a first switch sub-circuit, a second switch sub-circuit, adrive sub-circuit and a light-emitting device, and the drive sub-circuitincludes a drive transistor. The first switch sub-circuit is connectedto a data line for controlling the sub-pixel, a first gate line of thegate lines and a gate electrode of the drive transistor, and isconfigured to output a data voltage provided by the data line to thegate electrode of the drive transistor under a control of the first gateline. The second switch sub-circuit is connected to a read line, asecond gate line of the gate lines and a second electrode of the drivetransistor, and is configured to output a voltage of the secondelectrode of the drive transistor to the read line under a control ofthe second gate line. A first electrode of the drive transistor isconnected to a first voltage end, the second electrode of the drivetransistor is further connected to an anode electrode of thelight-emitting device, and a cathode electrode of the light-emittingdevice is connected to a second voltage end.

In some embodiments, the first switch sub-circuit includes a firsttransistor. A gate electrode of the first transistor is connected to thefirst gate line, a first electrode of the first transistor is connectedto the data line and a second electrode of the first transistor is tothe gate electrode of the drive transistor.

In some embodiments, the second switch sub-circuit includes a secondtransistor. A gate electrode of the second transistor is connected tothe second gate line, a first electrode of the second transistor isconnected to the second electrode of the drive transistor, and a secondelectrode of the first electrode is connected to the read line.

In some embodiments, the drive sub-circuit further includes a storagecapacitor. A first end of the storage capacitor is connected to theelectrode gate of the drive transistor, and an opposite end is connectedto the second electrode of the drive transistor

In some embodiments, the display panel further includes a plurality ofgate detection terminals disposed in the wiring area. Each gatedetection terminal is connected to a first gate line or a second gateline of the gate lines, and the gate detection terminals are configuredto receive gate signals output from the detection device.

In another aspect, a detection system is provided, and the detectionsystem includes any one of the display panels described above and adetection device. The detection device includes at least one sourcedriver electrically connected to the pad groups in the display panel.

In some embodiments, the at least one source driver includes a pluralityof the source drivers arranged side by side. The source drivers are inone-to-one correspondence with the drive groups in the display panel,and each source driver is connected to data detection terminals in a padgroup corresponding to a corresponding drive group.

In some embodiments, the display panel includes read signal terminals.Each source driver is electrically connected to read lines connected topixel circuits of sub-pixels in a drive group corresponding to thesource driver via read signal terminals.

In some embodiments, the detection device further includes a pluralityof gate drivers arranged side by side. The display panel includes gatedetection terminals, and each gate driver is connected to a plurality ofgate detection terminals of the gate detection terminals arrangedsequentially. Gate detection terminals electrically connected to any twoof the plurality of gate drivers are different.

In another aspect, a method for detecting any one of the display panelsdescribed above is provided. The display panel includes read lines,first gate lines and second gate lines, and pixel circuits of sub-pixelsinclude drive transistors. The method includes: outputting gate signalsto the first gate lines and the second gate lines row by row; receivingsequentially data voltages output by the detection device by a pluralityof data detection terminals in the pad groups, when a first gate lineand a second gate line receive gate signals; receiving a reset voltageoutput from the detection device by a read line, when one of datadetection terminals in each of the pad groups receives a data voltage;collecting a voltage of second electrode of drive transistor by the readline, and outputting the voltage via the read detection terminal whenthe drive transistor is cut off.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings described herein are used to provide a furtherunderstanding of the present disclosure and constitute a part of thepresent disclosure. The illustrative embodiments and descriptions serveto explain the present disclosure, but do not constitute a limitation tothe present disclosure. In the accompanying drawings:

FIG. 1a is a schematic structural diagram of a display panel accordingto some embodiments of the present disclosure;

FIG. 1b is a region division diagram of a display panel according tosome embodiments of the present disclosure;

FIG. 2 is a schematic structural diagram of another display panel basedon the structure shown in FIG. 1a according to some embodiments of thepresent disclosure;

FIG. 3 is a schematic diagram showing a connection relationship betweenread lines and sub-pixels in FIG. 2;

FIG. 4 is a schematic diagram showing a connection relationship betweendata lines and data detection terminal in FIG. 2;

FIG. 5 is a schematic diagram showing a connection relationship betweenshort wirings and data lines in FIG. 4;

FIG. 6 is a schematic structural diagram of the pixel circuit of thesub-pixel in FIG. 1 a;

FIG. 7 is a schematic structural diagram of a detection system accordingto some embodiments of the present disclosure; and

FIG. 8 is a flowchart of a method for detecting a display panelaccording to some embodiments of the present disclosure.

DETAILED DESCRIPTION

Technical solutions in embodiments of the present disclosure will bedescribed clearly and completely with reference to the accompanyingdrawings in the embodiments of the present disclosure. Obviously, thedescribed embodiments are merely some but not all embodiments of thepresent disclosure. All other embodiments made on the basis of theembodiments of the present disclosure by a person of ordinary skill inthe art without paying any creative effort shall be included in theprotection scope of the present disclosure.

In the preparation process of an OLED or LED display device, it isnecessary to detect threshold voltages of some Thin Film Transistors(TFTs), such as drive transistors, in a display panel of the displaydevice after a vacuum align process, to detect whether this displaypanel is qualified.

In related art, a detection device is electrically connected to each ofthe data lines in the display panel through a corresponding probe toimplement the detection of the threshold voltages described above.However, as the Pixels Per Inch (PPI) of the panel increases gradually,the number of the data lines also increases greatly, resulting in asmall distance between two adjacent data lines. For example, for a UltraHigh Definition Television (UHD) display panel, the number of the datalines can reach 3840×(4+1)=19200. In this case, the distance between twoadjacent data lines is about 15 μm. At this time, 19,200 probes need tobe in contact with 19,200 data lines in one-to-one correspondence toelectrically connect the detection device to the data lines through theprobes during the detection process. In this way, a problem ofmisalignment of probes may occur, thereby reducing the accuracy of thedetection result.

Regarding the above problem, some embodiments of the present disclosureprovide a display panel 01. The display panel is for example an OLEDdisplay panel or a LED display panel. As shown in FIG. 1b , the displaypanel 01 is for example divided into a display area 60 and a writingarea 61 around the display area 60. Alternatively, the display panel 01has a display area 60 and a writing area 61 around the display area 60.As shown in FIG. 1a , the display panel includes M drive groups 10arranged side by side in the display area 60, and each drive group 10includes a plurality of columns of pixel units 100. Each pixel unit 100includes N sub-pixels 101, where N≥3, M≥2, and M and N are positiveintegers.

It will be noted that, in some embodiments, one column of pixel units100 refer to a group of pixel units 100 composed of pixel units 100 towhich the plurality of sub-pixels 101 connected to a same data line DLbelong. As can be seen from the above description, one pixel unit 100includes N sub-pixels 101, and thus one column of pixel units 100include N columns of sub-pixels 101; and each column of sub-pixels 101is connected to a same data line DL.

In this case, the pixel units 100 in the one column of pixel units 100are for example vertically arranged in a matrix or in other shapes, andthe arrangement shape of the one column of pixel units is not limited inthe present disclosure, but all of the likely arrangement shapes of onecolumn of pixel units 100 are within the range of the presentdisclosure.

In some embodiments, N=3, i.e., each pixel unit 100 includes threesub-pixels 101. The three sub-pixels 101 are for example a red (R)sub-pixel, a green (G) sub-pixel and a blue (B) sub-pixel, respectively,as shown in FIG. 1a . Alternatively, the three sub-pixels 101 are a cyansub-pixel, a magenta sub-pixel and a yellow sub-pixel, respectively.

In some other embodiments, N=4, i.e., each pixel unit 100 includes foursub-pixels 101. The four sub-pixels 101 are for example a red (R)sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel and a white (W)sub-pixel, respectively. Alternatively, the four sub-pixel 101 are a red(R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel and a yellow(Y) sub-pixel, respectively.

In some embodiments, sub-pixels connected to the same data line DL arein the same color, that is, the color of the same column of sub-pixels101 is the same.

The above description is merely examples of the configuration of thesub-pixels 101 in a pixel unit 100, and the present disclosure is notlimited thereto.

Based on this, as shown in FIG. 1a , the display panel 01 furtherincludes M pad groups 20 disposed in the wiring area 61. Each pad group20 includes N data detection terminals 201 each of which is configuredto receive a signal, such as a data voltage Vdata, output by a detectiondevice 02 (shown in FIG. 6).

In some embodiments, each data detection terminal 201 is a pad. The datadetection terminal 201 is capable of being electrically connected withthe detection device 02 by contacting a probe of the detection device02. In addition, the pad groups 20 are in one-to-one correspondence withthe drive groups 10. Sub-pixels 101 emitting light of the same color ina drive group 10 are electrically connected to a data detection terminal201 of a corresponding pad group 20 through a same data line DL.

In some embodiments, as shown in FIG. 7, the detection device 02includes at least one source driver (IC) 50, and each source driver 50is for example electrically connected to a plurality of data detectionterminals 201 of a pad group 20 corresponding to a drive group 10 via aplurality of probes, so that the source driver 50 may provide the datavoltages Vdata for the data detection terminals 201. After the datadetection terminals 201 receive the data voltages Vdata, the datadetection terminals 201 transmit the data voltages Vdata to the datalines DL which are electrically connected to the data detectionterminals 201.

It can be seen from the above that the number of data detectionterminals 201 included in a pad group 20 is N, and the number ofsub-pixels 101 of one pixel unit 100 in a drive group 10 correspondingto the pad group 20 is also N. In this case, for example, in the casewhere one pixel unit 100 in a drive group 10 includes three sub-pixels101 (for example, R, G, B), the pad group 20 corresponding to the drivegroup 10 includes three data detection terminals 201, as shown in FIG.1a . One data detection terminal 201 (R) is configured to beelectrically connected with all red (R) sub-pixels 101 in the drivegroup 10, another data detection terminal 201 (G) is configured to beelectrically connected with all green (G) sub-pixels 101 in the drivegroup 10, and yet another data detection terminal 201 (B) is configuredto be electrically connected with all blue (B) sub-pixels 101 in thedrive group 10.

Alternatively, for example, in the case where one pixel unit 100 in adrive group 10 includes four sub-pixels 101 (for example, R, G, B, W),the pad group 20 corresponding to the drive group 10 includes four datadetection terminals 201, as shown in FIG. 2. One data detection terminal201 (R) is configured to be electrically connected with all red (R)sub-pixels 101 in the drive group 10, another data detection terminal201 (G) is configured to be electrically connected with all green (G)sub-pixels 101 in the drive group 10, yet another data detectingterminal 201 (B) is configured to be electrically connected with allblue (B) sub-pixels 101 in the drive group 10, and yet another datadetection terminal 201 (W) is configured to be electrically connectedwith all white (W) sub-pixels 101 in the drive group 10.

In summary, one pad group 20 corresponds to one drive group 10, and thesub-pixels 101 of the same color in the drive group 10 are connected toa data detection terminal 201 of the pad group 20 through the data linesDL. The number N of the detection terminals 201 in the pad group 20 isequal to the number N of the sub-pixels 101 in the pixel unit 100, so asto ensure that the sub-pixels 101 of each color in a drive group 10 areelectrically connected to the same data detection terminal 201 in acorresponding pad group 20.

Based on this, one source driver 50 in the detection device 02 maycorrespond to one drive group 10. In this case, one source driver 50 inthe detection device 02 may be electrically connected to itscorresponding drive group 10 by respectively connecting N probes, suchas only three probes shown in FIG. 1a , to three data detectionterminals 201 of one pad group 20. In this way, there is no need todirectly connect probes to data lines DL, thereby reducing the number ofthe probes. In addition, by increasing the distance between two adjacentdata detection terminals 201 in each pad group 20, the purpose ofincreasing the distance between two adjacent probes may also beachieved. Therefore, the probability of misalignment of probes may bereduced, thereby improving the accuracy of detection of thresholdvoltage.

In some embodiments, in order to realize the detection of the thresholdvoltages of drive transistors Md in the sub-pixels 101, as shown in FIG.2, the display panel 01 further includes a plurality of read detectionterminals 30 disposed in the wiring area 61. Furthermore, the displaypanel 01 includes a plurality of read lines RL.

Each read line RL is connected to one of the plurality of read detectionterminal 30. The read line RL is configured to collect the thresholdvoltages or mobility of the drive transistors Md in the sub-pixels 101connected with the read line RL, and output it to the detection device02 through the read detection terminal 30.

In this way, the read detection terminals 30 may be connected to thedetection device 02 through probes, so that the detection device mayreceive the threshold voltages collected by the read lines RL.

In some embodiments, in order to reduce the number of wirings in thedisplay area and to improve the aperture ratio, as shown in FIG. 3,pixel circuits of sub-pixels 101 in a same pixel unit 100 are connectedto a same read line RL. In this way, it is not necessary to connect eachsub-pixel 101 to a read line RL, thereby reducing the number of wiringsin the display area.

In this case, the process of detecting the threshold voltage will bedescribed by taking an example in which the threshold voltage of a drivetransistor is detected.

For a pixel unit 100, the sub-pixels 101 of different colors in thepixel unit 100 are for example detected at different times.

In some embodiments, N=4, i.e., each pixel unit 100 includes foursub-pixels 101, and data voltages Vdata are sequentially supplied to thedata lines DL electrically connected to four data detection terminals201 of one pad group 20 via the four data detection terminals 201. Forexample, as shown in FIG. 2, data voltages Vdata are supplied to thedata lines DL electrically connected to the four data detectionterminals 201 of one pad group 20 from left to right via the datadetection terminals 201.

In this case, during the process of scanning the sub-pixels 01 row byrow, the data line DL connected to one column of red (R) sub-pixels mayfirst receive the data voltage Vdata. At this time, a red (R) sub-pixelof the one column of red sub-pixels in the scanned row of the sub-pixels101 is detected, and the threshold voltage collected by the read line RLis the threshold voltage of the drive transistor Md in the red (R)sub-pixel of the row of sub-pixels 101.

Next, the data lines DL respectively connected to one column of green(G) sub-pixels, one column of blue (B) sub-pixels, and one column ofwhite (W) sub-pixels sequentially receive the data voltages Vdata. Atthis time, a green (G) sub-pixel, a blue (B) sub-pixel, and a white (W)sub-pixel in the scanned row of sub-pixels 101 are sequentiallydetected, so that the detection device 02 sequentially receives thethreshold voltages of the drive transistors Md in the green (G)sub-pixel, the blue (B) sub-pixel, and the white (W) sub-pixel in thescanned row of sub-pixels 101 via a same read line RL.

It can be seen from the above that multiple data lines DL need to beelectrically connected to one data detection terminal 201 of the padgroup 20. In order to electrically connect the data lines DL with thedata detection terminal in the pad group 20, in some embodiments, asshown in FIG. 4, the display panel 01 includes a plurality of shortwirings 202 disposed in the wiring area 61.

For example, one end of each short wiring 202 is connected to a datadetection terminal 201 of the pad group 20, and an opposite end isconnected to a data line DL connected to the sub-pixels 101 having thesame color in the drive group 10. In this case, a data detectionterminal 201 of a pad group 20 may be electrically connected to a dataline DL through a short wiring 202. At this time, there is no need toexcessively extend the length of the data line DL in the wiring area 61.

The short wirings 202 and the data lines DL are for example disposed indifferent layers. In this case, the data lines DL do not need to formcorners to in the case where they connect with the data detectionterminals 201, so that the number of the corners in the wiring area maybe reduced, which reduce the risk of tip discharge.

Based on this, the display panel 01 further includes gate lines GLdisposed in the display area 60, which intersect the data lines DL. Theshort wirings 202 and the gate lines are for example of the samematerial and in the same layer. In this way, the preparation of theshort wirings 202 may be completed while the gate lines GL are formed.

Alternatively, in order to directly connect the data lines DL with thedata detection terminals 201, in some other embodiments, the length ofthe data lines DL in the wiring area 61 are extended.

It will be noted that the above-mentioned sub-pixels 101 are delimitedby the intersections of the gate lines GL and the data lines DL.Therefore, the data lines DL connected to the sub-pixels 101 refer todata lines for delimiting the sub-pixels 101.

The preparation process of the display panel 01 will be detailed belowby taking the display panel 01 being an OLED display panel as anexample.

First, as shown in FIG. 5, a gate metal layer is deposited on a basesubstrate 110, and then a single patterning process is performed for thegate metal layer to form a plurality of gate lines GL and the shortwirings 202.

In some embodiments, the patterning process refers to a processincluding a photolithographic technology, or including both of thephotolithographic technology and an etching step, or further includingtechnology for forming a predetermined pattern such as printing, inkjetor the like. The photolithographic technology refers to a technology forforming a pattern by using photoresist, mask, exposure machine and thelike, and including technology such as film formation, exposure,development, etc. The patterning process can be chosen according to thestructures formed in the embodiments of the present disclosure.

The single pattering process is described by taking an example in whichdifferent exposure regions are formed by a single mask exposure process,and then a removal process such as multiple etching, ashing and the likeis performed for the different exposure regions to finally obtain thedesired pattern.

Next, a gate insulation layer GI 111 and a semiconductor active materiallayer are deposited on the base substrate 110 on which gate lines GL andshort wirings 202 have been formed. Then semiconductor active layers(IGZO) of TFTs in pixel circuits of sub-pixels 101 are formed byperforming a patterning process for the semiconductor active materiallayer.

Next, an etch stop material layer 112 is formed on the base substrate110 on which the above-mentioned structure has been formed, and apatterning process is performed for the etch stop material layer 112 toform a etch stop layer (ESL) over the semiconductor active layer of theTFT. The etch stop layer is configured to protect the semiconductoractive layer during the fabrication of the source electrode and thedrain electrode of the TFT.

Next, the etch stop material layer 112 is photoetched at the positionscorresponds to the short wirings 202, and then the gate insulating layer111 is etched by a dry etching process at the positions, to finally formvia holes 113.

Next, a data metal layer is deposited on the base substrate 110 on whichthe above-mentioned structure has been formed, and then a patterningprocess is performed for the data metal layer to form data lines DL. Thedata lines DL are connected with the short wirings 202 through the viaholes 113, thereby being electrically connected with the data detectionterminals 201 of the pad groups 20 by the short wirings 202.

At last, a passivation layer (PVX) 114 is formed on the base substrate110 on which the above structure has been formed, and an organiclight-emitting layer (EL), a hole layer, an electron layer, and the likefor constituting an OLED device are formed on a surface of thepassivation layer 114 facing away from the base substrate 110.

In addition, in some embodiments, a color filter layer is formed on thebase substrate 100 on which the organic light-emitting layer has beenformed, for realizing color display when the organic light-emittinglayer in the OLED panel is used for emitting white light.

In addition, in some embodiments, in order to finish the preparation ofthe OLED device, a cathode layer composed of transparent conductivematerial, such as ITO is formed, and an insulation layer is formed on aside of the cathode layer close to the base substrate 110.

The exemplary structure of a pixel circuit of each sub-pixel 101 will bedescribed below.

In some embodiments, as shown in FIG. 6, the pixel circuit includes afirst switch sub-circuit 41, a second switch sub-circuit 42, a drivesub-circuit 43 and a light-emitting device L. The drive sub-circuit 43includes a drive transistor.

The first switch sub-circuit 41 is connected to a data line DL fordelimiting the sub-pixel 101, and a first gate line GL1, and isconnected to a gate electrode of the drive transistor Md. The firstswitch sub-circuit 41 is configured to output the data voltage Vdatafrom the data line DL to the gate electrode of the drive transistor Mdunder the control of the first gate line GL1.

For example, the first switch sub-circuit 41 includes a first transistorT1, or a plurality of first transistors T1 in parallel.

A gate electrode of the first transistor T1 is connected to the firstgate line GL1, a first electrode is connected to the data line DL, and asecond electrode is connected to the gate electrode of the drivetransistor Md.

In addition, the second switch sub-circuit 42 is connected to a readline RL, a second gate line GL2 and a second electrode of the drivetransistor Md. The second switch sub-circuit 42 is configured to outputthe voltage of the second electrode of the drive transistor Md to theread line RL under the control of the second gate line GL2.

For example, the second switch sub-circuit 42 includes a secondtransistor T2, or a plurality of second transistors T2 in parallel.

A gate electrode of the second transistor T2 is connected to the secondgate line GL2, a first electrode of the second transistor T2 isconnected to the second electrode of the drive transistor Md, and asecond electrode of the second transistor T2 is connected to the readline RL.

In addition, a first electrode of the drive transistor Md is connectedto a first voltage terminal VDD, and the second electrode of the drivetransistor Md is also connected to an anode electrode of thelight-emitting device L. A cathode electrode of the light-emittingdevice L is connected to a second voltage terminal VSS.

On the basis of this, the drive sub-circuit 43 further includes astorage capacitor C, a first end of which is connected to the gateelectrode of the drive transistor Md, and an opposite end is connectedto the second electrode of the drive transistor Md.

It will be noted that the transistors described above are for exampleN-type transistors, or P-type transistors. The first electrode of eachof the transistors is a drain electrode, and the second electrode is asource electrode. Alternatively, the first electrode of each of thetransistors described above is a source electrode, and the secondelectrode is a drain electrode. Hereinafter, the embodiments aredescribed by taking the transistors being N-type transistors as anexample.

Based on this, by taking the pixel circuit shown in FIG. 6 as anexample, the method for detecting the threshold voltage Vth of the drivetransistor Md in the pixel circuit through the above read line RLincludes the following steps.

First, high level is output via the first gate line GL1 and the secondgate line GL2 to turn on the first transistor T1 and the secondtransistor T2 respectively.

In this case, the data voltage Vdata, which is equal to 3V, input viathe data line DL is written into the gate electrode (namely node A) ofthe drive transistor Md through the first transistor T1. At this time,the gate voltage Vg of the drive transistor Md meets: Vg=V_(A)=Vdata.

It will be noted that the above description is based on the example ofthe data voltage Vdata being equal to 3V. The value of the data voltageVdata is not limited herein, and can be configured by a person skilledin the art according to the time between the turn-on and cut-off of thedrive transistor Md in the display panel 01.

In addition, the read line RL is connected to an analog-to-digitalconverter (ADC) in the detection device 02, so that the reset voltage,such as 0V, is written into the source electrode (namely node B) of thedrive transistor Md by the detection device 02 via the second transistorT2. At this time, the source voltage Vs of the drive transistor Mdmeets: Vs=V_(B)=0V.

In some embodiments, a gate switch is provided between the ADC and theread line RL to control the electrically connection or disconnectionbetween the ADC and the read line RL through the gate switch.

Next, the drive transistor Md is turned on to start charging the readline RL. After a charge time, the gate source voltage Vgs of the drivetransistor Md meets: Vgs=Vth, and then the drive transistor Md is cutoff. At this time, the voltage on the read line RL is the source voltageVs of the drive transistor Md, and meets: Vs=Vg−Vth, so that thethreshold voltage Vth of the drive transistor Md is detected through theread line RL.

In this case, the read line RL is connected to a digital-to-analogconverter (DAC) in the detection device 02, thereby outputting thethreshold voltage Vth of the drive transistor Md read by the read lineRL to the detection device 02 to complete the detection for thethreshold voltage Vth of the drive transistor Md in the pixel circuit.

In some embodiments, a gate switch is provided between the DAC and theread line RL to control the electrically connection or disconnectionbetween the DAC and the read line RL through the gate switch.

It can be seen from the above that, in order to increase the apertureratio of the display area, sub-pixels 101 in a same pixel unit 100 isconnected to a same read line RL. In this case, the sub-pixels 101 inthe pixel unit 100 may sequentially receive the data voltages Vdataprovided via the different data lines DL, so that the threshold voltagesVth of the drive transistors Md in the sub-pixels 101 in the pixel unit100 may be detected separately. The detection process is the same asabove, and will not be described herein.

Further, each row of the sub-pixels 101 is connected to a first gateline GL1 and a second gate line GL2. The gate signals are supplied tofirst gate lines GL1 and second gate lines GL2 of the sub-pixels 101 rowby row during the detection process.

The light-emitting device L is for example an OLED device. In this case,the display panel 01 is an OLED display panel. Alternatively, thelight-emitting device L is an LED or a Micro-LED, and in this case, thedisplay panel 01 is a LED display panel.

On the basis of this, in some embodiments, in the case where the displaypanel 01 includes the first gate lines GL1 and the second gate linesGL2, as shown in FIG. 7, the display panel 01 further includes aplurality of gate detection terminals 31 disposed in the wiring area 61,and each gate detection terminal 31 is connected to a first gate lineGL1 or a second gate line GL2. The gate detection terminals 31 areconfigured to receive the gate signals output by the detection device02. For example, the detection device 02 includes gate drivers (GateICs) 51 which are capable of providing gate signals to the gatedetection terminals 31.

Some embodiments of the present disclosure provide a detection system,and the detection system includes any one of the display panels 01 asdescribed above and a detection device 02. The detection device 02includes at least one source driver 50 connected to the pad groups 20 inthe display panel 01. In this case, the detection device 02 isconfigured to output signals, such as the data voltages Vdata, to thedata detection terminals 201 of the pad groups 20 via the at least onesource driver 50.

In addition, as shown in FIG. 7, the detection device 02 furtherincludes a plurality of gate drivers 51 arranged in orders. In the casewhere the display panel 01 includes gate detection terminals 31, each ofthe gate drivers 51 is electrically connected to a plurality of gatedetection terminals 31 arranged in orders, and the gate detectionterminals 31 electrically connected to any two of the gate drivers 51are different, so that the gate drivers 51 may supply the gate signalsto the first gate lines GL1 and the second gate lines GL2.

On the basis of this, it can be seen from above that the detectiondevice 02 is also connected to the read detection terminals 30, so as toreceive the collected signals from the read lines RL via the detectionterminals 30.

In summary, the detection device 02 is configured to provide signals tothe data lines DL, the first gate lines GL1 and the second gate linesGL2 in the display panel 01 so as to make the pixel circuits of thesub-pixels in the display panel 01 operate, and to collect the thresholdvoltages of the drive transistors Md in the pixel circuits through readlines RL. Then, the collected threshold voltages are compared with areference value. In the case where the differences between one or acertain number of collected threshold voltages of the collectedthreshold voltages and the reference value are large and not incompliance with regulations, the display panel detected by the detectiondevice 02 is determined to be unqualified, thereby achieving the purposeof detecting the unqualified product.

In some embodiments, the detection device 02 includes a plurality ofsource drivers 50 arranged side by side. The source drivers 50 are inone-to-one correspondence with the drive groups 10 in the display panel,and each of the source drivers 50 is electrically connected to datadetection terminals 201 in a pad group 20 corresponding to the drivegroup 10.

For example, in a 4K display panel with a resolution of 4096×2160, thedisplay area is divided into 20 drive groups 10. In this case, 20 sourcedrivers 50 are arranged side by side in the detection device 02, andeach of the source drivers 50 is electrically connected to one pad group20 through probes, so that one source driver 50 corresponds to one drivegroup 10, and electrically connected to the plurality of columns ofpixel units 100 in the drive group 10.

The above detection system has the same advantageous effects as thedisplay panel provided in the foregoing embodiments, and details are notdescribed herein again.

Further, in the case where the display panel includes read signalterminals 30, the source driver 50 is electrically connected to the readlines RL in the drive group 10 corresponding to the source driver 50 viathe read signal terminals 30. That is, the sub-pixels 101 connected tothe read lines RL connected to the same source driver 50 are all in thesame drive group 10, thereby separately analyzing the threshold voltagescollected from the sub-pixels of the different drive groups 10.

In some embodiments, the short wirings 202 and the pad groups 20 in thedisplay panel are cut off after completing the detection of thethreshold voltages Vth. In addition, in the drive bonding process, thesource driver chip is bonded to a bonding pad 32 in FIG. 7.

Some embodiments of the present disclosure provide a method fordetecting any one of the display panels described above. The displaypanel 01 includes the read lines RL, the first gate lines GL1, and thesecond gate lines GL2, and the pixel circuits of the sub-pixels 101include drive transistors Md. As shown in FIG. 8, the method includessteps 101-104 (S101-S104).

In S101, gate signals are output to the first gate lines GL1 and thesecond gate lines GL2 shown in FIG. 7 row by row.

In some embodiments, the TFTs of the sub-pixels connected to the gatelines are N-type transistors, and the gate signals are high level.

In S102, a plurality of data detection terminals 201 in the pad groups20 sequentially receive data voltages Vdata output by the detectiondevice 02 when a first gate line GL1 and a second gate line GL2 receivethe gate signals.

For example, the first row of sub-pixels 101 is taken as an example.When the first gate line GL1 and the second gate line GL2 connected tothe first row of sub-pixels 101 receive the gate signals, for a drivegroup 10, the data detection terminal 201 connected with the red (R)sub-pixel in the drive group 10 may receive the above data voltage Vdatafirst, and then the data detection terminals 201 respectively connectedwith the green (G) sub-pixel, the blue (B) sub-pixel and the white (W)sub-pixel in the drive group 10 may successively receive the above datavoltages Vdata in the case where the pad group 20 includes four datadetection terminals 201 as shown in FIG. 7.

In S103, a reset voltage output by the detection device 02 is receivedby a read line RL when one of the data detection terminals 201 in eachof the pad groups 20 receives the data voltage Vdata.

For example, when the data detection terminal 201 connected to the red(R) sub-pixels in a drive group 10 receives the data voltage Vdata (forexample, 3 V), the read line RL connected to the red (R) sub-pixel inthe drive group 10 receives the reset voltage output from the detectiondevice 02, such as 0V, so that the gate voltage Vg of the drivetransistor Md in the pixel circuit of the red (R) sub-pixel shown inFIG. 6 is 3 V, and the source voltage Vs is 0 V.

In S104, the read line RL collects the voltage of the second electrodeof the drive transistor Md, namely the source voltage Vs when the drivetransistor Md is cut off, wherein the voltage meets: Vs=Vg−Vth, andoutputs it through the read detection terminal 30. In this case, thepurpose of detecting the threshold voltages of the drive transistors Mdmay be achieved.

It will be noted that when the data detection terminals 201 respectivelyconnected to the green (G) sub-pixels, the blue (B) sub-pixels and thewhite (W) sub-pixels in the drive group successively receive the datavoltage Vdata, the detection process of the threshold voltages in thesub-pixels of each color are the same as described above, and detailsare not described herein again.

In addition, the method for detecting the display panel provided by theembodiments of the present disclosure has the same beneficial effects asthe display panel provided by the foregoing embodiments, and details arenot described herein again.

The above embodiments are only exemplary embodiments of the presentdisclosure, but the protection scope of the present disclosure is notlimited thereto, and any person skilled in the art can easily think ofvariations or replacements within the technical scope disclosed by thepresent disclosure, which are intended to be covered by the protectionscope of the present disclosure. Therefore, the scope of protection ofthe present disclosure should be determined by the scope of the claims.

What is claimed is:
 1. A display panel comprising: M drive groups disposed side by side in a display area, each drive group comprising a plurality of columns of pixel units, and each pixel unit comprising N sub-pixels, wherein, N is greater than or equal to 3, M is greater than or equal to 2, and M and N are positive integers; and M pad groups disposed in a wiring area around the display area, each pad group comprising N data detection terminals, wherein each data detection terminal is configured to receive a signal output from a detection device, wherein the pad groups are in one-to-one correspondence with the drive groups, sub-pixels having same color in a drive group of the drive groups are electrically connected to a data detection terminal of one of the pad groups corresponding to the drive group via data lines, and a plurality of read detection terminals disposed in the wiring area, and a plurality of read lines, wherein each read line is connected to one of the plurality of read detection terminals, wherein pixel circuits of sub-pixels in each pixel unit is connected to a same read line, the read line is configured to collect threshold voltages of drive transistors in the pixel circuits, and output the threshold voltages to the detection device via a corresponding read detection terminal, and wherein a pixel circuit of each sub-pixel in the display area comprises a first switch sub-circuit, a second switch sub-circuit, a drive sub-circuit and a light-emitting device, and the drive sub-circuit comprises a drive transistor, wherein the first switch sub-circuit is connected to a data line for controlling the sub-pixel, a first gate line of the gate lines and a gate electrode of the drive transistor, and is configured to output a data voltage provided by the data line to the gate electrode of the drive transistor under a control of the first gate line, the second switch sub-circuit is connected to a read line, a second gate line of the gate lines and a second electrode of the drive transistor, and is configured to output a voltage of the second electrode of the drive transistor to the read line under a control of the second gate line, and a first electrode of the drive transistor is connected to a first voltage end, the second electrode of the drive transistor is further connected to an anode electrode of the light-emitting device, and a cathode electrode of the light-emitting device is connected to a second voltage end.
 2. The display panel according to claim 1, further comprising a plurality of short wirings disposed in the wiring area, wherein an end of each short wiring is connected to a corresponding one of the data detection terminals, and an opposite end is connected to a corresponding one of data lines.
 3. The display panel according to claim 2, further comprising gate lines disposed in the display area, wherein the gate lines and the data lines intersect, and are in a same layer and of a same material.
 4. The display panel according to claim 1, wherein, the first switch sub-circuit comprises a first transistor; a gate electrode of the first transistor is connected to the first gate line, a first electrode of the first transistor is connected to the data line and a second electrode of the first transistor is to the gate electrode of the drive transistor.
 5. The display panel according to claim 1, wherein, the second switch sub-circuit comprises a second transistor; a gate electrode of the second transistor is connected to the second gate line, a first electrode of the second transistor is connected to the second electrode of the drive transistor, and a second electrode of the first electrode is connected to the read line.
 6. The display panel according to claim 1, wherein, the drive sub-circuit further comprises a storage capacitor, a first end of the storage capacitor is connected to the electrode gate of the drive transistor, and an opposite end is connected to the second electrode of the drive transistor.
 7. The display panel according to claim 1, further comprising a plurality of gate detection terminals disposed in the wiring area, wherein each gate detection terminal is connected to a first gate line or a second gate line of the gate lines, and the gate detection terminals are configured to receive gate signals output from the detection device.
 8. A detection system, comprising a detection device and the display panel according to claim 1, wherein, the detection device comprises at least one source driver electrically connected to the pad groups in the display panel.
 9. The detection system according to claim 8, wherein, the at least one source driver comprises a plurality of source drivers arranged side by side, the source drivers are in one-to-one correspondence with the drive groups in the display panel, and each source driver is connected to data detection terminals in a pad group corresponding to a corresponding drive group.
 10. The detection system according to claim 9, wherein, the display panel comprises read signal terminals, each source driver is electrically connected, via read signal terminals, to read lines connected to pixel circuits of sub-pixels in a drive group corresponding to the source driver.
 11. The detection system according to claim 8, wherein, the detection device further comprises a plurality of gate drivers arranged side by side; the display panel comprises gate detection terminals, each gate driver is connected to a plurality of gate detection terminals of the gate detection terminals arranged sequentially; gate detection terminals electrically connected to any two of the plurality of gate drivers are different.
 12. A method for detecting the display panel according to claim 1, the display panel comprising read lines, first gate lines and second gate lines, pixel circuits of sub-pixels comprising drive transistors, and the method comprising: outputting gate signals to the first gate lines and the second gate lines row by row; sequentially receiving, by a plurality of data detection terminals in the pad groups, data voltages output by the detection device when a first gate line and a second gate line receive gate signals; receiving a reset voltage output from the detection device by a read line when one of data detection terminals in each of the pad groups receives a data voltage; collecting a voltage of a second electrode of a drive transistor by the read line, and outputting the voltage via a read detection terminal when the drive transistor is cut off. 